VHDL



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ae ccoo epeeo C aaaec aee, xpaeec B. C oo oea B C yaa a o o e oe. aaee pcaae ce o D ae cooecyx oe oca origin. o ee aee oea, a oop yaae D, o e aee D. ', . . A . , , . accop cey ae. package mem_helper is subtype mem_word is bit_vector (0 to 31); type page is array (0 to 16#FFF#) of mem_word; type page_pointer is access page; type sparse_memory is array (0 to 16#FFF#)of page_pointer; end mem_helper; page ec acco 4096 eeo, a oopx ec 32 oo epeeo a bit_vector ( word oe pyo ece). a ee a page_pointer oea a sparse _memory coep ccooe aee, yaaee a oe a page. c ce cpa pacpeee a, o oe sparse_memory oe xpa coepoe 16- eacoo a - ooe 24 ooe apeccoe pocpaco (c 12 o apeco cpa 12 o apeco yp cpa). e e eee, cope ceo p o oepoa ye cooac oo aa ac ooo apecoo pocpaca. cae, o o ye pacpee a o cpa oo oa, oa o eoxo. e pee ae o opopa ypae a oeo. use mem_helper_all; package mem_type is subtype mem is sparse_memory; subtype word is mem_word; procedure store (VM: inout mem; loc: address; contents: word); procedure retrieve (VM: inout mem; loc: address; signal value: out word); end mem_type; oe aea mem_type coepac o o sparse _memory mem_word, a ae poeypa coxpae coa ax epeeo a mem y, occaaaa p aoeoe aee.