VHDL



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, o e aaa ooex opae, x oee cae eoxooc cooa aea RAM_helper ae, a mem_type . Defs , address IntVal. accop, a opao o ae oe cooa. use mem_type.all; variable sys_mem:mem; . . . wait until mem_request='1'; if read_write='1' then -- a apoc. epea a y ax -- coepoe a retrieve (sys_mem,address_bus,data_bus); else -- ac. oxpa eyee aee a data_bus -- a store (sys_mem, address_bus, data_bus); end if; ee aea oo e caoe c eo aea cyae, ec oe aea oe ae-o opopa. ea ao x opopa oa oc cooecye ee aea. y store retrieve opeee ee aea mem_type. package body mem_type is procedure store (VM: inout mem; loc: address; contents: word) is constant page_no:natural: IntVal (loc (0 to 11)); constant page_addr: natural:= IntVal (loc (12 to 24)); begin if VM (page_no)= null then VM(page_no)= new page'(0 to 16#FFF# => X"00000000"); end if; VM (page_no)(page_addr):= contents; end store; procedure retrieve (VM:inout mem; loc: address; signal value:out word) is constant page_no: natural:= IntVal (loc (0 to 11)); constant page_addr: natural:= IntVal (loc (12 to 24)); begin if VM(page_no)= null then value<= X"00000000"; else value<= VM (page_no)(page_addr); end if; return; end retrieve; end mem_type; VM , contents loc. contents loc , , VM inout. poeype store coyec y IntVal pcoe aaoo ae ocae page_no. o aaoe aee ec e co, coaa co cap a apeca. ocae page_addr pcaaec aaoe aee aeoe a a.